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february 2009 rev 4 1/22 22 l6390 high-voltage high and low side driver features high voltage rail up to 600 v dv/dt immunity 50 v/nsec in full temperature range driver current capability: ? 290 ma source, ? 430 ma sink switching times 75/35 nsec rise/fall with 1 nf load 3.3 v, 5 v ttl/cmos inputs with hysteresis integrated bootstrap diode operational amplifier for advanced current sensing comparator for fault protections smart shut down function adjustable dead-time interlocking function compact and simplified layout bill of material reduction effective fault protection flexible, easy and fast design applications motor driver for home appliances, factory automation, industrial drives. hid ballasts, power supply units. description the l6390 is a high-voltage device manufactured with the bcd ?off-line? tech nology. it is a single chip half-bridge gate driver for n-channel power mosfet or igbt. the high side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos/ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp. the ic embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control. an integrated comparator is available for protections against over-current, over-temperature, etc. so - 16 d ip - 16 table 1. device summary order codes package packaging l6390 dip-16 tube l6390d so-16 tube L6390D013TR so-16 tape and reel www.st.com
contents l6390 2/22 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 cboot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l6390 block diagram 3/22 1 block diagram figure 1. block diagram uv detection level shifter bootstrap driver s v cc lvg driver hin lin hvg driver hvg boot out lvg uv detection op+ op- gnd opout sd/od dt opamp dead time r logic shoot through prevention sd latch floating structure comparator + v ref cp+ 1 2 11 14 15 16 7 5 8 3 4 10 9 6 smart sd from lvg vcc vcc 5v + - + - 5v
pin connection l6390 4/22 2 pin connection figure 2. pin connection (top view) table 2. pin description pin n # pin name type function 1lin i low side driver logic input (active low) 2sd /od (1) 1. the circuit provides less than 1 v on the lvg and hvg pins (@ isink = 10 ma), with v cc > 3 v. this allows omitting the ?bleeder? resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driv er assures low impedance also in sd condition. i/o shut down logic input (active low)/open drain (comparator output) 3 hin i high side driver logic input (active high) 4 vcc p lower section supply voltage 5 dt i dead time setting 6 op- i opamp inverting input 7 opout o opamp output 8 gnd p ground 9 op+ i opamp non inverting input 10 cp+ i comparator input 11 lvg (1) o low side driver output 12, 13 nc not connected 14 out p high side (floating) common voltage 15 hvg (1) o high side driver output 16 boot p bootstrap supply voltage hin sd/od lin vcc 1 3 2 4nc out hvg boo t 16 15 14 13 opout op- dt cp+ lvg nc 12 11 10 9 5 7 6 8 op+ gnd
l6390 truth table 5/22 3 truth table note: x: don't care table 3. truth table input output sd lin hin lvg hvg lxxll hhl l l hlhll hllhl hhhlh
electrical data l6390 6/22 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 14, 15 and 16 is guaranteed up to 1 kv (human body model) 4.2 thermal data table 4. absolute maximum rating symbol parameter value unit min max v cc supply voltage - 0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage - 0.3 620 v v hvg high side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low side gate output voltage - 0.3 v cc + 0.3 v v op+ opamp non-inverting input - 0.3 v cc + 0.3 v v op- opamp inverting input - 0.3 v cc + 0.3 v v cp+ comparator input voltage - 0.3 v cc + 0.3 v v i logic input voltage - 0.3 15 v v od open drain voltage - 0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t a = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 5. thermal data symbol parameter so-16 dip-16 unit r th(ja) thermal resistance junction to ambient 155 100 c/w
l6390 electrical data 7/22 4.3 recommended operating conditions table 6. recommended operating conditions symbol pin parameter test condition min max unit v cc 4 supply voltage 12.5 20 v v bo (1) 1. v bo = v boot - v out 16-14 floating supply voltage 12.4 20 v v out 14 dc output voltage - 9 (2) 2. lvg off. vcc = 12.5 v logic is operational if v boot > 5 v refer to an2738 for more details 580 v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c
electrical characteristics l6390 8/22 5 electrical characteristics 5.1 ac operation table 7. ac operation electrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test condition min typ max unit t on 1 vs 11 3 vs 15 high/low side driver turn-on propagation delay v out = 0 v v boot = v cc c l = 1 nf v i = 0 to 3.3 v see figure 3. 125 200 ns t off high/low side driver turn-off propagation delay 125 200 ns t sd 2 vs 11, 15 shut down to high/low side driver propagation delay 125 200 ns t isd comparator triggering to high/low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cp+. 200 250 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 dead time setting range (1) r dt = 0, c l = 1 nf, c dt = 100 nf 0.1 0.18 0.25 s r dt = 37 k , c l = 1 nf, c dt = 100 nf 0.48 0.6 0.72 s r dt = 136 k , c l = 1 nf, c dt = 100 nf 1.35 1.6 1.85 s r dt = 260 k , c l = 1 nf, c dt = 100 nf 2.6 3.0 3.4 s mdt matching dead time (2) r dt = 0, c l = 1 nf, c dt = 100 nf 80 ns r dt = 37 k , c l = 1 nf, c dt = 100 nf 120 ns r dt = 136 k , c l = 1 nf, c dt = 100 nf 250 ns r dt = 260 k , c l = 1 nf, c dt = 100 nf 400 ns t r 11, 15 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 on page 9 2. mdt = | dt lh - dt hl | see figure 5 on page 13
l6390 electrical characteristics 9/22 figure 3. timing figure 4. typical dead time vs. dt resistor value hin hvg 50% 10% 90% 50% t r t f t on t off 90% 10% lin lvg 50% 10% 90% 50% t r t f t on t off 90% 10% lvg/hvg sd 90% 50% t f t sd 10% 5gwn2kp '7xv ? $ssur[lpdwhgirupxodiru 5gwfdofxodwlrqw\s 5gw>n @ a'7>?v@
electrical characteristics l6390 10/22 5.2 dc operation table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) symbol pin parameter test condition min typ max unit low supply voltage section v cc_hys 4 v cc uv hysteresis 1200 1500 1800 mv v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+=op+=gnd; op-=5 v 120 150 a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+=op+=gnd; op-=5 v 720 1000 a v ref internal reference voltage 500 540 580 mv bootstrapped supply voltage section (1) v bo_hys 16 v bo uv hysteresis 1200 1500 1800 mv v bo_thon v bo uv turn on threshold 10.6 11.5 12.4 v v bo_thoff v bo uv turn off threshold 9.1 10 10.9 v i qbou undervoltage v bo quiescent current v bo = 9 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+=op+=gnd; op-=5 v 70 110 a i qbo v bo quiescent current v bo = 15 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+=op+=gnd; op-=5 v 150 210 a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 a r ds(on) bootstrap driver on resistance (2) lvg on 120 driving buffers section i so 11, 15 high/low side source short circuit current v in = v ih (t p < 10 s) 200 290 ma i si high/low side sink short circuit current v in = v il (t p < 10 s) 250 430 ma
l6390 electrical characteristics 11/22 logic inputs v il 1, 2, 3 low logic level voltage 0.8 v v ih high logic level voltage 2.25 v v il_s 1, 3 single input voltage lin and hin connected together and floating 0.8 v i hinh 3 hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl 1 lin logic ?0? input bias current lin = 0 v 3 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a i sdh 2 sd logic ?1? input bias current sd = 15 v 10 40 100 a i sdl sd logic ?0? input bias current sd = 0 v 1 a 1. v bo = v boot - v out 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 16 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) (continued) symbol pin parameter test condition min typ max unit
electrical characteristics l6390 12/22 table 9. opamp characteristics (v cc = 15 v, t j = +25 c) symbol pin parameter test condition min typ max unit v io 6, 9 input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (1) 100 200 na v icm input common mode voltage range 0v v ol 7 low level output voltage r l = 10 k to v cc 75 150 mv v oh high level output voltage r l = 10 k to gnd 14 14.7 v i o output short circuit current source, v id = +1; v o = 0 v 16 30 ma sink, v id = -1; v o = v cc 50 80 ma sr slew rate v i = 1 4 v; c l = 100 pf; unity gain 2.5 3.8 v/ s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k 70 85 db svr supply voltage rejection ratio vs. v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the direction of input current is out of the ic. table 10. sense comparator characteristics (v cc = 15 v, t j = +25 c) symbol pin parameter test conditions min typ max unit i ib 10 input bias current v cp+ = 1 v 1 a v ol 2 open drain low level output voltage i od = - 3 ma 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k resistor 90 130 ns sr 2 slew rate c l = 180 pf; r pu = 5 k 60 v/ sec
l6390 waveforms definitions 13/22 6 waveforms definitions figure 5. dead time and interlocking waveforms definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
smart shut down function l6390 14/22 7 smart shut down function l6390 integrates a comparator committed to the fault sensing function. the comparator has an internal voltage reference v ref connected to the inverting input, while the non-inverting input is available on pin 10. the comparator input can be connected to an external shunt resistor in order to implement a simple over-current detection function. the output signal of the comparator is fed to an integrated mosfet with the open drain output available on pin 2, shared with the sd input. when the comparator triggers, the device is set in shut down state and both its outputs are set to low level leaving the half-bridge in tri-state. figure 6. smart shut down timing waveforms hin/lin hvg/lvg sd/od open drain gate (internal) upper threshold lower threshold comp vref cp+ protection fast shut down: the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold real disable time 2 1 1 2 = (r on_od // r sd ) c sd = r sd c sd sd/od from/to controller v bias smart sd logic c sd r sd r on_od shut down circuit time constants
l6390 smart shut down function 15/22 in common over-current protection architectu res the comparator output is usually connected to the sd input and an rc network is connected to this sd /od line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. differently from the common fault detection systems, l6390 smart shut down architecture allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off. in fact the time delay between the fault and the outputs turn off is no more dependent on the rc value of the external network connected to the pin. in the smart shut down circuitry, the fault signal has a preferential path which directly switch off the outputs after the comparator triggering. at the same time the internal logic turns on the open drain output and holds it on until the sd voltage goes below the sd logic input lower threshold. the smart shut down system provides the possibility to increase the time constant of the external rc network (that is the disable time after the fault event) up to very large values without increasing the delay time of the protection. any external signal provided to the sd pin is not latched and can be used as control signal in order to perform, for instance, pwm chopping through this pin. in fact when a pwm signal is applied to the sd input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa.
typical application diagram l6390 16/22 8 typical application diagram figure 7. application diagram uv detection level s hifter boot s trap driver s v cc lvg driver v cc hin lin hvg driver hvg boot h.v. to load out lvg c b oot uv detection + - op+ op- gnd opout s d/od dt opamp dead time r logic s hoot through prevention floating s tructure + - comparator + v ref cp+ s d latch 5v 1 2 11 14 15 16 7 5 8 3 4 10 9 6 s mart s d from lvg + from controller from controller from/to controller to adc v bia s v bia s vcc vcc 5v
l6390 bootstrap driver 17/22 9 bootstrap driver a bootstrap circuitry is needed to supply the hi gh voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 8. a). in the l6390 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with diode in series, as shown in figure 8. b. an internal charge pump ( figure 8. b) provides the dmos driving voltage. 9.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: equation 2 c boot >>> c ext e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage and quiescent losses. e.g.: hvg steady state consumption is lower than 200 a, so if hvg t on is 5 ms, c boot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ). at low frequency this drop can be neglected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: equation 3 c ext q gate v gate ------------- - =
bootstrap driver l6390 18/22 where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: equation 4 v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 8. bootstrap driver v drop i ch e arg r dson v drop q gate t ch e arg ------------------ r dson == v drop 30nc 5 s -------------- - 120 0.7v ? = to load d99in1067 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot boot v cc v cc out out boot
l6390 package mechanical data 19/22 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 9. dip-16 mechanical data and package dimensions dip16 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 outline and mechanical data
package mechanical data l6390 20/22 figure 10. so-16 narrow mechanical data and package dimensions dimensions ref. mm inch min. typ. max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.004 0.008 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s 8 (max.) package and packing information so-16 weight: not available 16-lead small outline package outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s8 (max.) (1) "d" and "f" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (.006inc.) so16 (narrow) 0016020 d
l6390 revision history 21/22 11 revision history table 11. document revision history date revision changes 29-feb-2008 1 first release 09-jul-2008 2 updated: cover page, table 2 on page 4 , table 3 on page 5 , section 4 on page 6 , section 5 on page 8 , section 9.1 on page 17 17-sep-2008 3 updated test condition values on ta bl e 8 and ta b l e 9 17-feb-2009 4 updated table 7 on page 8 , table 8 on page 10 , table 9 on page 11 added table 4 on page 9
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